Process and arrangement for transmitting system-specific data in a synchronous microprocessor system

ABSTRACT

The process and arrangement enable the target-oriented and thereby collision-free transmission of data (addressing and useful data) via a synchronous system bus (SB syn ) in a microprocessor system (μPS), given data accesses of a microprocessor (μP) of the microprocessor system (μPS) to peripheral apparatuses (SP, DAC, AE) of the microprocessor (e.g. a memory, a digital-analog circuit, a display) that are system-compatible and system-incompatible with respect to data transmission protocols (e.g. I 2 C protocol). A control signal (SS), e.g. fashioned as a chip select signal, is transmitted on a separate control line (SL) between the microprocessor (μP) and the system-incompatible apparatus (AE) for the selection of the system-compatible and system-incompatible peripheral apparatuses (SP, DAC, AE) of the microprocessor (μP). Free addresses are respectively assigned to the system-compatible and the system-incompatible apparatuses (SP, DAC, AE).

BACKGROUND OF THE INVENTION

The invention relates to a method for transmitting system-specific datain a synchronous microprocessor system, and an arrangement fortransmitting the system-specific data in the synchronous microprocessorsystem.

A microprocessor system is the functional unit consisting of amicroprocessor, a memory, and a control unit for peripheral equipment,said system being respectively built into a multiplicity of technicalapparatuses. The microprocessor is thereby a universally applicable andfreely programmable functional unit designated the central unit (CentralProcessing Unit CPU), and which contains the complete control andcomputing unit of the microprocessor system and is housed on or moreintegrated circuits (chip). The term peripheral equipment refers to suchdevices as can be connected to the microprocessor. The peripheralapparatuses of the microprocessor are divided, according to theirfunction, into peripheral memory equipment, input/output peripheralequipment, and peripheral control equipment. The peripheral memoryequipment thereby includes devices provided for the storage of extensivedatabases, e.g. magnetic layer storage units and magnetic bubblememories. The input/output peripheral equipment includes functionalunits for the input and output of data, e.g. printer, monitor, etc. Theperipheral control equipment includes apparatuses that supply peripheralinput/output equipment with control signals (apparatus management).

The microprocessor system indicated above is used for example intelecommunication terminal equipment of wireless telecommunicationsystems.

Wireless telecommunication systems of the type designated above aremessage systems with a remote data transmission path between a messagesource and a message sink for message processing and messagetransmission, in which

1) the message processing and message transmission can take place in apreferred direction of transmission (Simplex operation) or in bothdirections of transmission (duplex operation),

2) the message processing is analog or digital,

3) the message transmission via the remote data transmission path iswireless—e.g. according to various radio standards such as DECT, GSM,WACS or PACS, IS-54, PHS, PDC, etc. (cf. IEEE Communications Magazine,January 1995, pages 50-57; D. D. Falconer et al: “Time Division MultipleAccess Methods for Wireless Personal Communications”).

“Message” is a higher-order term that stands both for the meaningcontent (information) and also for the physical representation (signal).

Signals can thereby represent e.g.

(1) images

(2) spoken words

(3) written words

(4) encrypted words or images.

FIG. 1 shows, as a representative of the large number of wirelesstelecommunication systems, a DECT/GAP system in which, according to theDECT/GAP standard (Digital European Cordless Telecommunication; cf. (1):Nachrichtentechnik Elektronik 42 (1992) January/February no. 1, Berlin,DE; U. Pilger “Struktur des DECT-Standards,” pp. 23 to 29 in connectionwith ETSI publication ETS 300175-1 . . . , Oct. 9, 1992; (2): TelcomReport 16 (1993), no. 1, J. H. Koch: “Digitaler Komfort f{umlaut over(u)}r schnurlose Telekommunikation—DECT-Standard eröffmet neueNutzungsgebiete”, pages 26 and 27; (3): tec 2/93—Das technische Magazinvon Ascom “Wege zur universellen mobilen Telekommunikation”, pages 35 to42; Generic Access Profile; cf. ETSI Publication prETS 300444, April1995, Final Draft, ETSI, FR), at a DECT/GAP base station BS, via aDECT/GAP air interface designed for the frequency range between 1.88 and1.90 Ghz, a maximum of twelve connections according to the TDMA/FDMA/TDDmethod (Time Division Multiple Access/Frequency Division MultipleAccess/Time Division Duplex) are set up parallel to DECT/GAP mobileparts MT1 . . . MT12. The number 12 results from a number “k” of timeslots or, respectively, telecommunication channels provided for theduplex operation of a DECT/GAP system (k=12). The connections canthereby be internal and/or external. Given an internal connection, twomobile parts registered at the base station BS, e.g. the mobile part MT2and the mobile part MT3, can communicate with one another. For the setupof an external connection, the base station BS is connected with atelecommunication network TKN, e.g. in line-bound form via atelecommunication terminal unit TAE, or, respectively, a private branchexchange NStA, with a line-bound telecommunication network, or,according to WO 95/05040, in wireless form as a repeater station with ahigher-order telecommunication network. Given the external connection,with a mobile part, e.g. with the mobile part MT1, it is possible tocommunicate with a subscriber in the telecommunication network TKN viathe base station BS, the telecommunication terminal unit TAE, or,respectively, the private branch exchange NStA. If, as in the case ofthe Gigaset 951 (Siemens cordless telephone, cf. Telcom Report 16, 1993,no. 1, pages 26 and 27), the base station BS has only one terminal tothe telecommunication terminal unit TAE or, respectively, to the privatebranch exchange NStA, then only one external connection can be set up.If, as in the case of the Gigaset 952 (Siemens cordless telephone, cf.Telcom Report 16, 1993, no. 1, pages 26 and 27), the base station BS hastwo terminals to the telecommunication network TKN, then in addition tothe external connection with the mobile part MT1 a further externalconnection from a wire-bound telecommunication terminal apparatus TKEconnected to the base station BS is possible. In principle, it isthereby also conceivable that a second mobile part, e.g. the mobile partMT12, instead of the telecommunication terminal apparatus TKE, uses thesecond terminal for an external connection. According to thesubsequently published German Patent Application 195 45 762.5, themobile parts MT1 . . . MT12 are operated in manual operation (normaloperation) with a battery or an accumulator, and in hands-free operationare operated in connection with a charge station connected to a voltagenetwork SPN. The base station, fashioned as a wireless small switchinginstallation, is connected to the voltage network SPN via a networkterminal apparatus NAG.

FIG. 2 shows, on the basis of the reference Components 31 (1993), no. 6,pages 215-218; S. Althammer, D. Br{umlaut over (u)}ckmann:“Hochoptimierte IC's f{umlaut over (u)}r DECT-Schnurlostelefone,” thecircuit design of the base station BS and of the mobile part MT. Thebase station BS and the mobile part comprise, according to thereference, a radio part FKT with an antenna ANT allocated for thetransmission and reception of radio signals, a signal processing meansSVE, and a central control unit ZST, connected with one another in themanner shown. In the radio part FKT, essentially the known means, suchas transmitter SE, receiver EM, and synthesizer SYN, are contained.Among other things, a coding/decoding means CODEC is contained in thesignal processing means SVE. The central control unit ZST comprises,both for the base station BS and also for the mobile part MT, amicroprocessor μP, having a program module PGM constructed according tothe OSI/ISO layer model, a signal control part SST, and a digital signalprocessor DSP, connected with one another in the manner shown. Of thelayers defined in the layer model, only the first four layers,immediately essential for the base station BS and the mobile part MT,are shown. The signal control part SST is fashioned in the base stationBS as a time switch controller TSC and in the mobile part MT as a burstmode controller BMC. The essential difference between the two signalcontrol parts TSC, BMC is that the base-station-specific signal controlpart TSC takes over additional switching functions in relation to themobile-part-specific signal control part BMC. The microprocessor μP is,according to the definition indicated above, a component of amicroprocessor system.

The principle of the functioning of the switching units indicated aboveis described for example in the above-cited reference Components 31(1993), no. 6, pages 215-218.

The specified circuit design according to FIG. 2 is supplemented in thebase station BS and the mobile part MT by additional functional unitsaccording to their function in the DECT/GAP system according to FIG. 1.

The base station BS is connected with the telecommunication network TKNvia the signal processing means SVE and the telecommunication terminalunit TAE or, respectively, the private branch exchange NStA. As anoption, the base station BS can also comprise a user interface(functional units drawn in with dotted lines in FIG. 2), consisting forexample of an input means EE fashioned as a keyboard, a display means AEfashioned as a display, a speech/hearing means SHE fashioned as ahandset with microphone MIF and earpiece HK, as well as a tone call bellTRK.

The mobile part MT comprises the user interface, possible as an optionin the base station BS, with the above-described operating elementsbelonging to this user interface.

FIG. 3 shows a synchronous microprocessor system μPS, in which forexample the microprocessor μP according to FIG. 2 is connected withexternal peripheral equipment via a synchronous system bus SB_(syn) fordata transmission. The external apparatuses are for example a memory SPfashioned as a E²PROM and a digital-analog circuit DAC. The knownfunctioning of these external apparatuses in connection with themicroprocessor μP is not discussed in more detail.

The transmission of the data (addressing and useful data) between themicroprocessor μP and the external apparatuses SP, DAC on thesynchronous system bus SB_(syn) takes place in chronologicallysynchronized fashion or, respectively, according to a predetermined datatransmission pulse. For this purpose, the system bus SB_(syn) comprisestwo lines, a clock signal line TSL and a data line DL. The data arethereby transmitted according to an agreed-upon system-specificprotocol, which is in principle freely selectable. In the present case,this protocol is, according to the reference Funk-Technik 39 (1984), No.4, pages 162 through 166; Schmidt, W. P.: “Bussysteme-Verbindungenzwischen Zentral- und Peripherieschaltungen,” the I²C protocol, inwhich, according to FIG. 4, a START-Bit, an apparatus-specific address,the data, and a STOP-Bit are transmitted in the sequence named. For thisprotocol-specific transmission of the data, the microprocessor μPcomprises a control means STE (controller), which correspondinglysupports the data transmission on the synchronous system bus SB_(syn)fashioned as an I²C bus as a result of the agreed-upon protocol.

The above-specified arrangement “Microprocessor←→external apparatuses”can be regarded as a master-slave configuration, in which themicroprocessor μP can be designated the master apparatus ME and thememory SP can be designated the first slave apparatus SLE1 with a firstslave address SLA1 for the addressing, and the digital-analog circuitDAC can be designated as the second slave apparatus SLE2 with a secondslave address SLA2 for the addressing. Within this master-slaveconfiguration defined in this way, there are no compatibility problemsbetween “master” and “slave/slaves,” so that the two slave apparatusesSLE1, SLE2 are compatible with the master apparatus ME, i.e., aresystem-compatible.

FIG. 4 shows the signal curves that occur according to the I²Cspecification on the clock signal line TSL and on the data line DL.After the transmission of the START-Bits, the slave address SLA1, SLA2is sent. This is recognized by the memory SP and the digital-analogcircuit DAC as their own, so that, in accordance with sequence, thesubsequently transmitted data are interpreted/received by the memory SPand the digital-analog circuit DAC.

If a further external (peripheral) apparatus, e.g. a display means AEfashioned as a display, should in addition be allocated to themicroprocessor μP that proves to be system-incompatible in the sense ofthe above nomenclature, it was previously standard to connect thisincompatible display means AE with the microprocessor μP via separateadditional lines ZL between the microprocessor μP and the display meansAE and program-supported driver means TRM.

From the reference Electronics/Nov. 3, 1983, pages 162 and 163; R.Brawner, “Expanding the I/O facilities of the 8051 microcomputer,” adata transmission method and an arrangement therefor are specified inwhich the apparatuses connected to the bus are activated on respectivelyallocated control lines by means of “chip select” items of information.

The underlying object of the invention is that, in a synchronousmicroprocessor system, an apparatus that is system-incompatible inrelation to the system-specific data transmission can be supplied withapparatus-specific data in a simple manner without an additionalhardware outlay at the microprocessor.

In general terms the present invention is a method for transmittingsystem-specific data in a synchronous microprocessor system. Addressingdata and useful data are transmitted between a microprocessor and atleast one system-compatible system-specific apparatus, as well as atleast one system-incompatible system-specific apparatus, on a firstline. Clock signals are transmitted on a second line, the first andsecond lines forming a system bus. First addressing data and firstuseful data destined for the system-compatible apparatus are transmittedon the first line. Second addressing data and second useful datadestined for the system-incompatible apparatus are transmitted on thefirst line. Third addressing data, likewise destined for thesystem-incompatible apparatus, is transmitted on a control line betweenthe microprocessor and the system-incompatible apparatus. Free addressesare respectively assigned to the system-compatible apparatus and to thesystem-incompatible apparatus.

Advantageous developments of the present invention are as follows.

The first addressing data, the second addressing data, the first usefuldata and the second useful data are transmitted on a I²C bus accordingto an I²C protocol.

The third addressing data contains chip select information.

The system-compatible apparatus is an E²PROM.

The system-incompatible apparatus is an optical display device.

The method is utilized in a wireless hand apparatus of a wirelesstelecommunication system that operates according to a DECT/GAP standard.

The method is utilized in a wireless base station of a wirelesstelecommunication system that operates according to a DECT/GAP standard.

The method is utilized in a mobile radiotelephone hand apparatus of amobile radiotelephone telecommunication system that operates accordingto a GSM standard.

The method is utilized in a mobile radiotelephone base station of amobile radiotelephone telecommunication system that operates accordingto a GSM standard.

The present invention is also an arrangement for the transmission ofsystem-specific data in a synchronous microprocessor system. Thearrangement has the following components:

a microprocessor and at least one system-compatible system-specificapparatus as well as at least one system-incompatible system-specificapparatus, between which addressing data and useful data aretransmitted;

a system bus between the microprocessor and the system-compatibleapparatus as well as the system-incompatible apparatus, on which firstaddressing data and first useful data destined for the system-compatibleapparatus and second addressing data and second useful data destined forthe system-incompatible apparatus are transmitted on a first line, andclock signals are respectively transmitted on a second line;

a control line between the microprocessor and the system-incompatibleapparatus, on which third addressing data, likewise destined for thesystem-incompatible apparatus, is transmitted; and

free addresses being respectively assigned to the system-compatibleapparatus and to the system-incompatible apparatus.

The underlying idea of the invention is that, on the basis of themicroprocessor system indicated in the introduction to the specificationand the technical application thereof, in particular in wirelesstelecommunication systems, given data accesses of a microprocessor ofthe microprocessor system to peripheral apparatuses of themicroprocessor (e.g. a memory, a digital-analog circuit, a displaymeans) that are system-compatible and system-incompatible with respectto data transmission protocols (e.g. I²C protocol), data (addressing anduseful data) are transmitted via a synchronous system bus intarget-directed and thereby collision-free manner, in that

1) on a separate control line, a control signal, fashioned e.g. as achip select signal, is transmitted for the selection of thesystem-compatible and system-incompatible external (peripheral)apparatuses of the microprocessor, and

2) free addresses are respectively assigned to the system-compatible andsystem-incompatible apparatuses.

This has the advantage that no additional terminal contacts (pins) arerequired on the microprocessor (simplification of layout in-the chipdesign of the microprocessor). Moreover, the existing processorperformance can be optimally exploited.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the present invention which are believed to be novel,are set forth with particularity in the appended claims. The invention,together with further objects and advantages, may best be understood byreference to the following description taken in conjunction with theaccompanying drawings, in the several Figures of which like referencenumerals identify like elements, and in which:

FIG. 1 depicts a prior art DECT/GAP system;

FIG. 2 is a block diagram of a prior art base station and mobile part;

FIG. 3 depicts a prior art synchronous microprocessor system;

FIG. 4 shows signal curves in the FIG. 3 system;

FIG. 5 shows, on the basis of the known microprocessor system accordingto FIG. 3, a modified microprocessor system,

FIG. 6 shows the signal curves that occur according to the I²Cspecification on the clock signal line and the data line according toFIG. 5 for the data transmission between the microprocessor and thedisplay means,

FIG. 7 shows the signal curves that occur according to the I²Cspecification on the clock signal line and the data line according toFIG. 5 for the data transmission between the microprocessor and thememory or, respectively, digital-analog circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

On the basis of the microprocessor system μPS according to FIG. 3, FIG.5 shows a modified microprocessor system μPS_(m), in which thesystem-incompatible display means AE according to FIG. 3, like thesystem-compatible memory SP and the system-compatible digital-analogcircuit DAC according to FIG. 3, is connected with the microprocessor μPvia the synchronous system bus SB_(syn) and, in addition, via a singlecontrol line SL. In this way, the program-supported driver means TRM inthe microprocessor μP, required in the known microprocessor system μPSaccording to FIG. 3, can be omitted, and the additional lines ZL can bereplaced by the single control line SL.

For the trouble-free operation of the modified microprocessor systemμPs_(m), the following conditions must however be maintained on thesynchronous system bus SB_(syn):

a) accesses by the microprocessor μP to the system-compatibleapparatus(es) (memory SP, digital-analog circuit DAC) must not beinterpreted or, respectively, must not be able to be interpreted by thesystem-incompatible apparatus (display means AE), designated as thethird slave means (SLE3).

b) accesses by the microprocessor μP to the system-incompatibleapparatus(es) (display means AE) must not disturb the system-compatibleapparatuses (memory SP, digital-analog circuit DAC).

In order to meet both these conditions, the microprocessor μP of thecontrol means STE contains allocated control means STM, fashioned insuch a way that a data transmission is possible that is target-directedand thereby collision-free with respect to the accesses. This takesplace in that

1) on the control line SL, a control signal SS, fashioned as a chipselect signal, is transmitted for the selection of the system-compatibleand system-incompatible external (peripheral) means of themicroprocessor μP, and

2) a free virtual slave address or addresses SLA_(v) is/are assigned tothe system-incompatible apparatus(es), which address or addresseshas/have not yet been allocated to the other apparatuses.

In contrast to the driver means TRM according to FIG. 3, the controlmeans STM require no additional terminal contacts (pins) at themicroprocessor μP (simplification of layout in the chip design of themicroprocessor). Moreover, the existing control means STE can be used(optimal exploitation of the existing processor performance).

On the basis of FIG. 4, FIG. 6 shows the signal curves that occuraccording to the I²C specification on the clock signal line TSL and thedata line DL according to FIG. 5 for the data transmission between themicroprocessor μP and the display means AE. After the transmission ofthe start bit, the virtual slave address SLA_(v) is sent. This is notrecognized by the memory SP and the digital-analog circuit DAC as theirown, so that consequently the subsequently transmitted data are notinterpreted/received by the memory SP and the digital-analog circuitDAC. If the control signal SS is sent after the transmission of thevirtual slave address SLA_(v) and before the data transmission on thecontrol line SL (setting of the chip select signal to HIGH potential),the system-incompatible display means AE is thereby activated for thereception of the data subsequently transmitted on the system busSB_(syn).

On the basis of FIG. 4, FIG. 7 shows the signal curves occurringaccording to the I²C specification on the clock signal line TSL and thedata line DL according to FIG. 5 for the data transmission between themicroprocessor μP and the memory SP or, respectively, the digital-analogcircuit DAC. The response of the system-compatible memory SP or,respectively, of the system-compatible digital-analog circuit DAC takesplace as in FIG. 4. Due to the fact that the control signal SS is notsent on the control line SL (chip select signal at LOW potential), thesystem-incompatible display means AE is not activated. The subsequentlytransmitted data on the clock signal line TSL and the data line DL arethus not interpreted or, respectively, received by the display means AE.

The invention is not limited to the particular details of the method andapparatus depicted and other modifications and applications arecontemplated. Certain other changes may be made in the above describedmethod and apparatus without departing from the true spirit and scope ofthe invention herein involved. It is intended, therefore, that thesubject matter in the above depiction shall be interpreted asillustrative and not in a limiting sense.

What is claimed is:
 1. A method for transmitting system-specific data ina synchronous microprocessor system, comprising the steps of: a)transmitting addressing data and useful data between a microprocessorand at least one system-compatible system-specific apparatus, as well asat least one system-incompatible system-specific apparatus, on a firstline, and transmitting clock signals to both said system-compatiblesystem-specific apparatus and said system-incompatible system-specificapparatus on a second line, the first and second lines forming a systembus; b) transmitting first addressing data and first useful datadestined for the system-compatible apparatus on the first line; c)transmitting second addressing data and second useful data destined forthe system-incompatible apparatus on the first line, and transmittingthird addressing data, likewise destined for the system-incompatibleapparatus, on a control line between the microprocessor and thesystem-incompatible apparatus; and d) respectively assigning freeaddresses to the system-compatible and to the system-incompatibleapparatus.
 2. The method according to claim 1, wherein the firstaddressing data, the second addressing data, the first useful data andthe second useful data are transmitted on a I²C bus according to an I²Cprotocol.
 3. The method according to claim 1, wherein the thirdaddressing data contains chip select information.
 4. The methodaccording to claim 1, wherein the system-compatible apparatus is anE²PROM.
 5. The method according to claim 1, wherein thesystem-incompatible apparatus is an optical display device.
 6. Themethod according to claim 1, wherein the method is utilized in awireless hand apparatus of a wireless telecommunication system thatoperates according to a DECT/GAP standard.
 7. The method according toclaim 1, wherein the method is utilized in a wireless base station of awireless telecommunication system that operates according to a DECT/GAPstandard.
 8. The method according to claim 1, wherein the method isutilized in a mobile radiotelephone hand apparatus of a mobileradiotelephone telecommunication system that operates according to a GSMstandard.
 9. The method according to claim 1, wherein the method isutilized in a mobile radiotelephone base station of a mobileradiotelephone telecommunication system that operates according to a GSMstandard.
 10. An arrangement for the transmission of system-specificdata in a synchronous microprocessor system, comprising: amicroprocessor and at least one system-compatible system-specificapparatus as well as at least one system-incompatible system-specificapparatus, between which addressing data and useful data aretransmitted; a system bus between the microprocessor and thesystem-compatible apparatus as well as the system-incompatibleapparatus, on which first addressing data and first useful data destinedfor the system-compatible apparatus and second addressing data andsecond useful data destined for the system-incompatible apparatus aretransmitted on a first line, and clock signals to both saidsystem-compatible system-specific apparatus and said system-incompatiblesystem-specific apparatus are respectively transmitted on a second line;a control line between the microprocessor and the system-incompatibleapparatus, on which third addressing data, likewise destined for thesystem-incompatible apparatus, is transmitted; and free addresses beingrespectively assigned to the system-compatible apparatus and to thesystem-incompatible apparatus.
 11. The arrangement according to claim10, wherein the system bus is an I²C bus, on which the first addressingdata, the second addressing data, the first useful data and the seconduseful data are transmitted according to an I²C protocol.
 12. Thearrangement according to claim 10, wherein the third addressing datacontain chip select information.
 13. The arrangement according to claim10, wherein the system-compatible apparatus is an E²PROM.
 14. Thearrangement according to claim 10, wherein the system-incompatibleapparatus is an optical display device.
 15. The arrangement according toclaim 10, wherein the arrangement is utilized in a wireless handapparatus of a wireless telecommunication system constructed accordingto a DECT/GAP standard.
 16. The arrangement according to claim 10,wherein the arrangement is utilized in a wireless base station of awireless telecommunication system constructed according to a DECT/GAPstandard.
 17. The arrangement according to claim 10, wherein thearrangement is utilized in a mobile radiotelephone hand apparatus of amobile radiotelephone telecommunication system constructed according toa GSM standard.
 18. The arrangement according to claim 10, wherein thearrangement is utilized in a mobile radiotelephone base station of amobile radiotelephone telecommunication system constructed according toa GSM standard.